JET-ARCHER-1 · Carrier PCB Net List Rev 1.0 · 2026-05-23 Schematic capture target: KiCad 9.x This is a human-readable summary of the major nets. The authoritative netlist is generated by KiCad from the .kicad_sch project once schematic capture is complete. ═══════════════════════════════════════════════════════════════════════════════ POWER NETS ═══════════════════════════════════════════════════════════════════════════════ VBAT_RAW (22.2 V nominal, 19.8–25.2 V operational, up to 8 A) Source : J1.1 (XT60 +) Net : L1.1, D1.1 Note : ESC commutation noise present; LC filter before eFuse VBAT_PROT (22.2 V, post-eFuse, OCP @ 4 A, OVP @ 28 V) Source : U1.OUT (TPS25985 SW pin) Loads : U2.VIN (TPS548A20), TP1 Note : Post-eFuse rail. Hot-swap inrush limited. +5V_SOM (5.0 V ±2%, 8 A capable) Source : U2.SW → L2 → output node Loads : J2.VDD_IN (×14 pins ganged), U3.IN, U4.IN, U5.VBUS, U6.VCCA, J9.VBUS Decoup : C2, C3, C4 (220 µF poly) + C5, C6, C7, C8 (22 µF MLCC) Note : Primary SOM rail. Heavy copper polygon on L3 power plane. +3V3 (3.3 V ±3%, 300 mA) Source : U3.OUT (AP2204K-3.3) Loads : J5 (MAVLink ref), J6 (I2C ref), J7 (GPIO ref), J8 (debug ref), J3 (CSI ref), U6.VCCB (level shifter B-side) Decoup : C33 (1 µF), C9 (100 nF near U3) Note : Carrier-side 3.3 V CMOS reference +1V8_REF (1.8 V ±3%, 200 mA) Source : U4.OUT (TLV70218) Loads : Reserved for SOM-side level shift, currently NC test point Decoup : C35 (1 µF), C10 (100 nF) GND All ground returns. Continuous L2 plane. Stitching vias every 5 mm minimum around CSI/USB3/PCIe diff pairs. ═══════════════════════════════════════════════════════════════════════════════ SO-DIMM SOCKET (J2) — STRAPPING + RESET ═══════════════════════════════════════════════════════════════════════════════ MODULE_ID (J2.217) Pulled high via R9 (100 k to +5V_SOM) → enables 4.75–20 V VDD_IN range. NEVER tie to GND on this carrier (would lock to 5 V only). POWER_EN (J2.218) Active-high. Pull-up R6 (10 k to +5V_SOM). Drive low to hold SOM in reset; release to boot. Reserved for future GPIO from FC. SYS_RESET* (J2.219) Active-low. Pull-up R7 (10 k to +3V3). Released by carrier ~50 ms after VDD_IN stable. SHUTDOWN_REQ* (J2.220) Active-low. Pull-up R8 (10 k to +3V3). Reserved — drive low to request graceful shutdown. FORCE_RECOVERY* (J2.221) No-connect on carrier (jumper pad for bring-up; default NC). Short to GND to force USB recovery boot. ═══════════════════════════════════════════════════════════════════════════════ SO-DIMM SOCKET (J2) — PCIe Gen3 x4 → NVMe (J9) ═══════════════════════════════════════════════════════════════════════════════ PCIE0_REFCLK_P / N : J2.49/50 → J9.REFCLK_P/N PCIE0_TX0_P / N : J2.53/54 → J9.PERp0 / PERn0 PCIE0_RX0_P / N : J2.59/60 → J9.PETp0 / PETn0 PCIE0_TX1_P / N : J2.63/64 → J9.PERp1 / PERn1 PCIE0_RX1_P / N : J2.69/70 → J9.PETp1 / PETn1 PCIE0_TX2_P / N : J2.73/74 → J9.PERp2 / PERn2 PCIE0_RX2_P / N : J2.79/80 → J9.PETp2 / PETn2 PCIE0_TX3_P / N : J2.83/84 → J9.PERp3 / PERn3 PCIE0_RX3_P / N : J2.89/90 → J9.PETp3 / PETn3 PCIE0_PERST* : J2.45 → J9.PERST* PCIE0_CLKREQ* : J2.46 → J9.CLKREQ* PCIE0_WAKE* : J2.47 → J9.WAKE* Constraints: • 85 Ω diff impedance • Intra-pair skew ≤ ±5 mil • Inter-pair skew ≤ ±25 mil • Reference plane = L2 GND (continuous) • Stitching vias every 5 mm along pair edges ═══════════════════════════════════════════════════════════════════════════════ SO-DIMM SOCKET (J2) — USB 3.2 Gen2 → J4 ═══════════════════════════════════════════════════════════════════════════════ USB0_D_P / D_N : J2.111/112 → U5.D1/D2 → J4.D+ / D- USB0_SS_TX_P / TX_N : J2.115/116 → U5.SS_TX → J4.SSTX+ / SSTX- USB0_SS_RX_P / RX_N : J2.119/120 → U5.SS_RX → J4.SSRX+ / SSRX- USB0_VBUS_DET : J2.113 → +5V_SOM via R (1 k) USB0_OC* : J2.114 → NC Constraints: • 90 Ω diff impedance • USB3 SS lanes ≤ 4" total length • ESD on D+/D-/SS via U5 (TPD4S012) ═══════════════════════════════════════════════════════════════════════════════ SO-DIMM SOCKET (J2) — CSI-2 → J3 (FFC to capture bridge) ═══════════════════════════════════════════════════════════════════════════════ CSI0_CLK_P / N : J2.123/124 → J3.5/6 CSI0_D0_P / N : J2.127/128 → J3.7/8 CSI0_D1_P / N : J2.131/132 → J3.9/10 CSI0_D2_P / N : J2.135/136 → J3.11/12 CSI0_D3_P / N : J2.139/140 → J3.13/14 CSI0_I2C_SDA : J2.143 → J3.18 CSI0_I2C_SCL : J2.144 → J3.19 CSI0_GPIO_PWDN : J2.145 → J3.20 CSI0_GPIO_RST : J2.146 → J3.21 CSI0_3V3 : +3V3 → J3.1 CSI0_GND : GND → J3.2, J3.22 Constraints: • 100 Ω diff impedance • Intra-pair skew ≤ ±2 mil • Total length ≤ 6" • Routed on L4 to avoid L1 power planes ═══════════════════════════════════════════════════════════════════════════════ SO-DIMM SOCKET (J2) — UART → FC LINK (J5, MAVLink) ═══════════════════════════════════════════════════════════════════════════════ UART1_TXD : J2.203 → U6.A1 → U6.B1 → J5.3 (TX) UART1_RXD : J2.204 → U6.B2 → U6.A2 → J5.4 (RX) UART1_CTS* : J2.205 → U6.A3 → U6.B3 → J5.5 (CTS, optional) UART1_RTS* : J2.206 → U6.A4 → U6.B4 → J5.6 (RTS, optional) J5.1 : +5V_SOM (powers FC if needed) J5.2 : GND Constraints: • 3.3 V CMOS Jetson side, 3.3 V or 5 V FC side via U6 level shifter • 921600 baud nominal • ESD via 0402 TVS at J5 pads (optional) ═══════════════════════════════════════════════════════════════════════════════ SO-DIMM SOCKET (J2) — I2C → J6 (External IMU passthrough) ═══════════════════════════════════════════════════════════════════════════════ I2C0_SDA : J2.211 → J6.3 (with R12 4.7 k pull-up to +3V3) I2C0_SCL : J2.212 → J6.4 (with R13 4.7 k pull-up to +3V3) J6.1 : +3V3 J6.2 : GND ═══════════════════════════════════════════════════════════════════════════════ SO-DIMM SOCKET (J2) — GPIO → J7 (Arm signal + status) ═══════════════════════════════════════════════════════════════════════════════ GPIO00 (ARM_IN) : J2.197 → J7.3 GPIO01 (STATUS_OUT) : J2.198 → J7.4 → D2 (LED) via R10 J7.1 : +3V3 J7.2 : GND ═══════════════════════════════════════════════════════════════════════════════ DEBUG UART (J8) — Bring-up serial console ═══════════════════════════════════════════════════════════════════════════════ UART_DEBUG_TX : J2.207 → J8.3 UART_DEBUG_RX : J2.208 → J8.4 (with D4 reverse-polarity Schottky) J8.1 : +3V3 J8.2 : GND Note: Debug UART is the system console — connect to USB-UART adapter at 115200 8N1 for boot logs. ═══════════════════════════════════════════════════════════════════════════════ TEST POINTS ═══════════════════════════════════════════════════════════════════════════════ TP1 → VBAT_PROT TP2 → +5V_SOM TP3 → +3V3 TP4 → +1V8_REF TP5 → GND TP6 → UART1_TXD (carrier side, post level-shift) TP7 → UART1_RXD (carrier side, post level-shift) TP8 → CSI0_CLK_P ═══════════════════════════════════════════════════════════════════════════════ NET SUMMARY ═══════════════════════════════════════════════════════════════════════════════ Total nets (estimated) : ~140 Diff pairs : 19 (12 PCIe + 3 USB3 + 5 CSI-2) Single-ended high-speed : 0 Power rails : 4 (VBAT_RAW, VBAT_PROT, +5V_SOM, +3V3, +1V8) Used SO-DIMM pins : ~95 of 260 (remainder NC) ═══════════════════════════════════════════════════════════════════════════════ NETLIST GENERATION (from KiCad) ═══════════════════════════════════════════════════════════════════════════════ To produce a KiCad-format netlist from the schematic: kicad-cli sch export netlist \ --output JET-ARCHER-1.net \ --format kicadsexpr \ JET-ARCHER-1.kicad_sch To produce a PADS-format netlist (for tools that need it): kicad-cli sch export netlist \ --output JET-ARCHER-1.pads \ --format pads \ JET-ARCHER-1.kicad_sch PCBWay's assembly service uses the BOM + CPL CSV files (provided separately) rather than the netlist directly. The netlist is for layout sign-off and internal review.